Anuradha Agarwal on LinkedIn: Thanks for the terrific discussion, Sri Priya S.. And a huge shoutout to… (2024)

Thank you Dr. Linda K Molnar for your vision of a creating a circular economy in advanced materials, and thank you to the NSF Convergence Accelerator for this opportunity to make a positive impact in the world. Phase 2 funding challenges us to bring sustainable innovative solutions to the semiconductor industry value chain; solutions which can be adopted across the board by other industries, thus driving a circular economy. FUTUR-IC is meeting this challenge by co-optimizing across three inter-connected dimensions of Technology, Ecology, and Workforce. Co-optimization is critical for maintaining the exponential growth of performance and markets in the semiconductor industry, within ecologically acceptable constraints.

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Thank you to Laura Hiscott, Editor of PIC Magazine, for her insightful questions which led to this article ! And thank you to NSF Convergence Accelerator for funding this important work towards sustainability.https://lnkd.in/gaq6bGfu

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Thank you, Jorn Smeets. IPSR-International at MIT last week indeed offered an opportunity for timely discussions regarding sustainable (#NSFfunded) materials, devices, processes, and systems in electronic-photonic integration for new applications. This is a clear path to obtaining high microchip performance (high bandwidth, low latency), with a low environmental impact (PFAS-free alternatives, low energy consumption).

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Dont miss this upcoming webinar on the use of the silicon ntride material platform for sensing: Tuesday, June 4th from 12-1 pm EDT. https://lnkd.in/gKEDwK2S

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NSF Convergence Accelerator Program - FUTUR-IC #NSFfundedhttps://lnkd.in/gitt7Thw

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GRAND CHALLENGES ACROSS THE SEMICONDUCTOR VALUE CHAINIPSR-INTERNATIONAL 2024 SPRING MEETINGJune 5-7, 2024MIT, Room 6-120, Cambridge, MAThe IPSR-International: Integrated Photonics System Roadmap promotes synchronous, self-consistent solutions for the electronic-photonic manufacturing value chain. For the first time in more than 40 years, the semiconductor industry is confronted with limits to transistor size, to its environmental footprint, and to its workforce pipeline readiness. The ecological impact of exponential growth in performance and market size has introduced roadblocks for materials use, energy consumption and end-of-life disposal.FUTUR-IC is a global academic/industry alliance tasked to maintain continued progress of the Semiconductor Manufacturing and Information Systems industry with a 3-dimensional scaling paradigm for technology, ecology, and workforce solutions.The charter for this meeting is construction of the growth path for the next 40 years of Information Technology hardware, with concurrently engineered, technology-ecology-workforce solutions.REGISTRATION ENDS MAY 31st.https://lnkd.in/eZUEUaSD

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We are proud to have successfully conducted the first-ever hands-on electronic-photonic packaging boot camp for MassBay community college (MBCC) students at MIT.nano last week. This boot camp was part of an NSF-ATE funded program called NCAIST (Northeast Consortia for Advanced Integrated Silicon Technologies), through SUNY Poly, Albany.The instruction team belonged to the MIT Initiative for Knowledge and Innovation in Manufacturing (IKIM). The boot camp for MBCC students included a tour of MIT.nano (including the Cryo-EM tool explained by Jenn Podgorski), a hands-on electronic-photonic packaging (EPP) lab, lectures introducing photonic integrated circuit (PIC) device concepts, a deep dive into PIC applications, Virtual Reality simulations to learn about PIC devices and packaging tools, as well as a primer on microchip sustainability.Drew Weninger (PhD student of Prof. Lionel C. Kimerling in DMSE), presented a comparison of state-of-the-art electronic-photonic packaging technologies. He discussed innovations in this field, including his research on evanescent chip-to-chip passive assembly. He trained students on the die bonder located at the MIT.nano LEAP (Lab for Education and Application Prototypes) facility.Even before they entered the lab, students completed a Virtual Reality (VR) simulation of the die bonder tool to become familiar with the tool's software and hardware. Instruction on this tool simulation, as well as PIC device simulations were led by Dr. Sajan Saini, our education director, and Trevor Morrisey, our simulation software expert. Ira Fay, our education game designer was also in attendance. The VR device simulations allowed students to build their intuition about on-chip photon manipulation. Dr. Saini later introduced them to PIC applications.What was most gratifying to the instruction team were the questions asked by the students as they learned new concepts like confinement, evanescence, coupling, radial bending, and propagation/scattering losses, all as a function of device geometry, materials platform, polarization, and wavelength. We presented new ideas for microchip sustainability based on our research through NSF Convergence Accelerator’s FUTUR-IC project: how to design and build microchips with high performance while staying within environmental sustainability constraints. We were excited to host other leads of the NCAIST NSF-ATE program: Prof. Abraham Michelen, SUNY Polytechnic Institute, Albany; Prof. Marina Bograd, MassBay Community College; and Prof. Aimee Dalenta as well as Prof. Nicholas Massa, both from Springfield Technical Community College.The MassBay students are excited to be starting summer internships armed with this new EPP and PIC knowledge.Our IKIM team is grateful for this opportunity to share knowledge and train the next generation, for jobs in the microchip industry and beyond.Anu Agarwal, On behalf of The MIT-MBCC Boot Camp Instruction Team for the NCAIST NSF-ATE program

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The FUTUR-IC Global Alliance at MIT is excited to share that we have won Phase 2 of the NSF Convergence Accelerator Track I Program on Sustainable Materials for Global Challenges. FUTUR-IC is managed by MIT’s Materials Research Laboratory (MRL).The balance between human existence and microchip benefits is being severely challenged by a relentless and unsustainable appetite for electronics consumption. The FUTUR-IC Global Alliance for Sustainable Microchip Manufacturing creates self-consistent three dimensions of technology, ecology, and workforce solutions to sustain the continued progress of the semiconductor manufacturing and the information systems industry, which is confronted with limits to transistor size, to its environmental footprint, and to its workforce pipeline readiness. Good business requires multi-dimensional decisions based on the consequences for people, planet, and profits. Frontier constraints in the microchip industry are: 1) Technology/Profits: Enhanced microchip functionality for next generation applications such as AI, 6G, LiDAR etc. can no longer depend solely on shrinking the dimensions of a transistor; 2) Ecology/Planet: Net Zero environmental impact for a product life cycle is critical to life on earth; 3) Workforce/People: Leadership from a new green-literate innovative STEM workforce is required. Concurrently engineered solutions are expected to build a common learning curve to power the next 40 years of progress for the semiconductor industry.FUTUR-IC will: 1) Benefit consumers: Enhance life while targeting Net Zero environmental impact by 2050; 2) Foster future innovators and enhance full-spectrum workforce training: Extend green literacy in microchip technologies to recruit and retain from K-Gray; 3) Increase DEIA: Support diversity in leadership, gender, ethnicity, and cultural backgrounds, to ensure that research is informed by a broad range of perspectives to shape future technology trajectories; 4) Transform the global microchip supply chain: Provide coherent technology evolution within the constraints of the environmental and social impacts of materials, processes and designs.

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